PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
| PWMEN0 | When one, PWM mode is enabled for CT32Bn_MAT0. When zero, CT32Bn_MAT0 is controlled by EM0. |
| PWMEN1 | When one, PWM mode is enabled for CT32Bn_MAT1. When zero, CT32Bn_MAT1 is controlled by EM1. |
| PWMEN2 | When one, PWM mode is enabled for CT32Bn_MAT2. When zero, CT32Bn_MAT2 is controlled by EM2. |
| PWMEN3 | When one, PWM mode is enabled for CT32Bn_MAT3. When zero, CT32Bn_MAT3 is controlled by EM3. Note: It is recommended to use match channel 3 to set the PWM cycle. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |